In terms of improving chip performance, the advanced process route is to reduce the feature size of individual transistors and improve transistor integration at the same die size level (with the same design framework, chip performance/computing power is positively correlated with the number of transistors); However, advanced packaging cannot change the size of individual transistors, and can only improve system efficiency from the perspective of bringing the CPU closer to Memory and computing closer to memory, thereby improving the computing and memory efficiency of each computation. The second is to integrate more components within a single chip package: signal transmission speed sorting, Wafer>IC substrate>PCB, where the communication efficiency of components within the chip is higher than at the board level, improving chip performance at the system level.

In terms of chip lightweighting, advanced processes can achieve die size reduction by reducing the feature size of individual transistors without sacrificing the overall performance of the chip, while maintaining the same computational power and number of transistors; Advanced packaging, because it has no ability to miniaturize transistor size, can only achieve lightness and thinness through finer materials and denser structures. For example, the packaging of mobile phone AP processors often adopts the FCCSP packaging form, which includes a CSP carrier board. Fanout (TSMC collaborates with Apple, and Apple's A-series chips mostly use InFO technology packaging, i.e. Fanout) packaging, canceling the CSP carrier board (CSP carrier board is about 0.3 mm thick). The packaged chip is lighter and thinner, which significantly improves the overall (mobile phone) structural space margin.

In terms of both high-performance and thinness, advanced manufacturing processes can achieve a balance, while advanced packaging has trade-offs. For example, when Apple's A-series chips were upgraded from A10 to A11, the process was increased from 16 nm to 10 nm, the chip area was reduced from 125 mm2 to 88 mm2, and the number of transistor integrations increased from 3.3 billion to 4.3 billion; When upgrading the A-series chips from A13 to A14, the wafer process was upgraded from 7nm to 5nm, the chip area was reduced from 98 mm2 to 88 mm2, and the number of transistor integrations increased from 8.5 billion to 11.8 billion, achieving a balance between performance improvement and thinness. Advanced packaging, on the other hand, aims to improve chip performance because it has no effect on reducing transistor size. Improving performance involves increasing the collaborative efficiency of various components within the chip, and stacking more components in a system (essentially improving transistor data within the system). The cost is that the system volume and area are larger, which means that the cost of advanced packaging to improve performance is sacrificing thinness, while achieving thinness is sacrificing performance improvement.

Under the premise of technology availability, improving chip performance is the first choice for advanced process upgrades, while advanced packaging adds to the icing on the cake. What we usually see is that high-performance and high computing power chips will consider advanced packaging (2.5D, CoWoS, etc.), but these high computing power chips often also use advanced process technology. That is to say, advanced packaging/chiplet applications usually only appear in the packaging solution selection of top flagship chips, and are not a universal large-scale application solution. For example, the 7 nm AI training chip Siyuan 290 from the Cambrian period may adopt a "1+4" architecture, which is a chiplet packaging form with 1 CPU/GPU paired with 4 HBM storage. This chip is also one of the flagship chip products of the Cambrian period; The Huawei HiSilicon Ascend 910 chip adopts an advanced 7nm process technology. As can be seen from the promotional image, it also adopts a CoWoS structure with multiple stacked chips, which is also a form of chiplet. These chips are all based on advanced processes, and in order to further improve chip performance, CoWoS and other 2.5D advanced packaging technologies are adopted, indicating that advanced processes are superior to advanced packaging in terms of process route selection. Advanced processes are the first choice for upgrading chip performance, and advanced packaging is the icing on the cake.

In situations where advanced processes are unavailable, product performance is maintained through chip stacking (advanced sealing/chiplet) and computational architecture reconstruction. Taking the A-series chip parameters of Apple as an example, A12, A10, and A7 chips use 7 nm, 14/16 nm (Samsung 14 nm, TSMC 16 nm), and 28 nm processes respectively. A-series mobile phone AP chips typically have a die size of approximately 100 mm2. On this 100 mm2 chip, A12, A10, and A7 chips integrate approximately 6.9 billion, 3.3 billion, and 1 billion transistors, respectively. Next, we will conduct a simple arithmetic conversion and discuss how the process of reducing production can maintain the computing power of the chip. If the chip process is reduced from 7 nm to 14 nm, the 7 nm process integrates 6.9 billion transistors on the A12 chip. If the 14 nm process is used to try to achieve similar computing power, the first step is to ensure that the number of transistors is consistent with the A12 chip, which is~7 billion. Without considering the significant improvement in the performance of individual transistors due to process improvement, the 14 nm process chip requires an area twice that of the 7 nm process, which is~200 mm2; If the chip process is reduced from 7 nm to 28 nm, the A7 chip with reference to 28 nm only integrates 1 billion transistors. To achieve the number of 7 billion transistors, the chip area needs to be expanded to~700 mm2. The larger the chip area, the lower the process yield, and the higher the manufacturing cost of a single chip obtained in actual manufacturing. Therefore, in the context where advanced processes are not available, reducing the process and stacking chips can indeed reduce computational disadvantages to a certain extent. However, to stack more chips, larger IC boards, more Chiplet chips, and more packaging materials are required, which also leads to increased power consumption, volume/area, and cost due to outdated processes. Therefore, for example, by stacking two chips at 14 nm, the performance of a 7 nm chip with the same number of transistors can be achieved; By stacking multiple 28 nm chips, achieve 14 nm chip performance. This stacking scheme may have practical value in the fields of HPC (server, AI inference) and base station based large chips, but for consumer electronics such as mobile AP chips and wearable chips, chip stacking is difficult to implement under strict spatial volume constraints in their application scenarios.

VI Our country has very little reserve of advanced process production capacity, and advanced packaging/chiplets can help compensate for the scarcity of processes

The globalization of cutting-edge technology is dead, and the production capacity of advanced processes in mainland China is extremely scarce and scarce. According to different wafer sizes, the production capacity of 6-inch wafers in mainland China accounts for nearly half of the global total, while the production capacity of 12 inch wafers is only about 10% of the global total. According to different process statistics, processes above 90 nm in mainland China account for about 20% of the world's total, processes between 20-90 nm account for about 10% of the world's total, and processes below 20 nm only account for about 1% of the world's total. The proportion of high-end manufacturing processes in mainland China is low, and there are obvious shortcomings in the industrial structure, with great potential for future expansion. The investment in high-end process expansion is large, with an investment of about $10 billion per 10000 pieces of production capacity for 3 nm process chips, which is much higher than the investment of about $700 million per 10000 pieces of 28 nm process chips. To make up for the shortcomings in the wafer industry structure in mainland China, it is necessary to focus on investing in high-end process wafer manufacturing capacity. This requires both technical breakthroughs and substantial investment support, which is a long and arduous task.                                                                                                                                                     

Advanced packaging/Chiplet can release a portion of advanced process capacity for use in more urgent demand scenarios. From the above analysis, it can be seen that through process reduction and chip stacking, dependence on advanced processes can be reduced in some scenarios where there are no power and volume limitations, and chip costs are not sensitive. We can plan and apply the limited advanced process production capacity from a higher strategic perspective to the application needs that require more advanced processes.